Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI

Dynamic Threshold (DTMOS) circuits have been proposed as a circuit style for low-power VLSI systems that takes advantage of the independent body control in partially-depleted SOI. As SOI technologies have scaled, the increasing body capacitance and body resistance have limited the effectiveness of DTMOS circuits that drive the body at the same speed as the gate. An analysis of DTMOS in 0.13μm PD-SOI shows that a near-static body control independent of the gate is the lowest power DTMOS configuration, provides reduced delay and energy-delay-product over floating-body circuits, and allows for leakage control during low activity. Simulations show that DTMOS is effective at low power supply voltages when used in gates with large transistors, high fan-in, and/or high wire capacitance. Under these conditions, a delay improvement up to 40% while using 20% less energy than floating-body transistors can be